1. Technical Field
The present invention provides a pattern for testing a connected state of a semiconductor device, in particular, to a semiconductor chip package capable of detecting an open and a short.
2. Description of the Related Art
A conventional method for connecting a semiconductor chip to a substrate includes a wire bonding method and a flip chip bonding method. The wire bonding method adheres a chip to a lead frame, connects a pad of the chip to a terminal with a bonding wire, and seals them with a resin. Meanwhile, the flip chip bonding method adheres a chip to an epoxy or ceramic substrate, and forms a flip chip ball grid array package (FCB, hereinafter referred to as “flip chip package”) by using a solder ball as a terminal. In such a flip chip bonding method, an element (or a chip) is assembled in face down orientation onto a substrate. This flip chip bonding method has a high space efficiency, and is strong against electromagnetic interference even in a high frequency wave, because it uses thick and short connecting wires. Furthermore, performing a batch processing, the flip chip bonding method incurs less manufacturing cost than the wire bonding method. Even with all those merits, the flip chip bonding method is currently applied only in a micro processor operating at a gigahertz level, and a high speed logic IC for networks devices, since solder balls and pads, etc. are expensive. However, with increasing demands on a noise control, the flip chip bonding method is steadily substituting for the wire bonding method.
A semiconductor chip package using the wire bonding or flip chip bonding method needs a number of dispositions, solderings, and other processes. Accordingly, to improve the qualities of the semiconductor chip package, testing and inspection are necessary. Malfunctioning of the semiconductor chip package is mainly caused by its component chips, and bare boards during component-injecting processes or soldering processes. Examples of such malfunctions are wrong values or labels, poor circuit performances, open circuits, short circuits, wrong positioning of the components, physical damage, improper soldering, damaged or open lands, and out of tolerance condition. The descriptions below will focus on a forming method of a semiconductor chip package using the flip chip bonding method.
FIG. 1 shows a pattern for testing a connected state of a flip chip by using a daisy chain, in a flip chip connection testing semiconductor chip package according to a prior art. In FIG. 1 are illustrated a substrate 110, an array of substrate bumps 120, an array of element pads 130, and four measuring pads 140 formed around corners of the substrate 110.
The substrate 110 is a typical printed circuit board, and has a wiring formed according to a particular pattern. On the substrate 110 is formed an array of the substrate bumps 120. The substrate bump 120 is electrically connected with the element pad 130 formed in a semiconductor element. For convenience, the body of the semiconductor element is omitted in FIG. 1.
Here, in order to detect an open area between the substrate bump 120 and the element pad 130, the element pads 130 are electrically connected in pairs, and the substrate bumps 120 are electrically connected in pairs such that the pairs of the element pads 130 that are not electrically connected are now electrically connected with each other through the electrical connection of the pairs of the substrate bumps 120. With this, when the substrate bump 120 and the element pad 130 are normally connected with each other, an open can be detected by measuring a resistance between the measuring pads 140.
However, such a test pattern cannot detect a short. With advances in substrate technologies, more fine pitches are required, and thus the semiconductor chip package is more likely to have a short. Consequently, there has been a need for a test pattern detecting the short.